The present invention relates to a class D amplifier that amplifies square-wave signals which have undergone, for example, pulse width modulation (PWM) or pulse density modulation (PDM).
The present application claims priority from Japanese Application No. 2004-226928, the disclosure of which is incorporated herein by reference.
In recent years, simpler, smaller, and higher efficiency system configurations of audio systems performing digital signal processing have been strived for through the use of class D amplifiers. In these systems, the class D amplifiers amplify square-wave audio signals (so-called, 1-bit stream format audio signals) formed by pulse width modulation or pulse density modulation and directly supply them to speakers via a low-pass filter.
FIG. 1 is a schematic diagram that represents the configuration of a conventional class D amplifier applied to this type of digital audio system.
The class D amplifier in this figure is connected to a semiconductor integrated circuit device (IC) 1. Here, the IC 1 is equipped with a modulator 2 that converts analog input signals and PCM digital signals to 1-bit stream format signals Pin using pulse width modulation or pulse density modulation.
In other words, the semiconductor integrated circuit device 1 operates using two power supply voltages of positive power supply voltage +VL and negative power supply voltage −VL which are equal absolute potential relative to the ground potential (0 V) as a reference. In addition to the modulator 2, the device 1 includes waveform detectors 3a, 3b, excessive electric current detectors 4a, 4b, and amplifiers 5a, 5b. The amplifiers 5a and 5b amplify 1-bit stream format signals Pin and then output 1-bit stream format signals Pa and Pb (hereinafter, simply referred to as output modulated signals) respectively, to allow a P-channel field-effect transistor FETa and an N-channel field effect transistor FETb (described later) to operate in a push-pull manner.
The class D amplifier operates using two power supply voltages of positive power supply voltage +VH and negative power supply voltage −VH which are higher than power supply voltages +VL and −VL respectively, and are equal absolute potential relative to the ground potential as a reference. The class D amplifier comprises a power amplification zone formed from the P-channel field effect transistor FETa and the N-channel field effect transistor FETb, resistors 6a, 6b, RLa, and RLb, and Zener diodes 7a, 7b, 8a, 8b, 9a, and 9b. 
The Zener diodes 9a and 9b which generate equal Zener voltages each form a power supply voltage shifter. These shifters supply the respective power supply voltages +VL and −VL to the semiconductor integrated circuit device 1. The power supply voltages +VL and −VL have been lowered by respective Zener voltages so as to be lower than the positive power supply voltage +VH and the negative power supply voltage −VH supplied from a main power supply (not shown in the figure).
The transistors FETa and FETb are connected through respective resistors RLa and RLb between power supply terminals for the power supply voltages +VH and −VH. The push-pull operation of the transistors FETa and FETb, which follows drive signals Pga and Pgb, outputs a power-amplified, 1-bit stream format signal (hereinafter referred to as “an output modulated signal”) Pout. Thereafter, supplying this output modulated signal Pout to a low-pass filter composed of a coil 10 and a capacitor 11 converts the signal to analog audio signal Sout which is then output to a speaker, for example.
The resistors 6a and 6b are determined to be equal resistance values and the Zener diodes 7a and 7b are formed by Zener diodes which generate equal Zener voltages.
The resistor 6a and the Zener diode 7a, which form a bias voltage level shifter, apply a level shift (voltage bias) to the input modulated signal Pa based on the Zener voltage and that level-shifted drive signal Pga is supplied to the gate of the transistor FETa.
In other words, the Zener diode 7a generates the drive signal Pga, that varies within a voltage range between the ground potential and the power supply voltage +VH as shown in FIG. 2(b), by applying a positive voltage bias to the input modulated signal Pa, that varies within a voltage range between the ground potential (0 V) and the power supply voltage +VL as shown in FIG. 2(a), to adjust it to the bias condition of the transistor FETa that operates under the power supply voltage +VH.
In a similar manner, the resistor 6b and the Zener diode 7b, which form a bias voltage level shifter, apply a level shift (voltage bias) to the input modulated signal Pb based on the Zener voltage and that level-shifted drive signal Pgb is supplied to the gate of the transistor FETb.
In other words, the Zener diode 7b generates the drive signal Pgb, that varies within a voltage range between the ground potential and the power supply voltage −VH as shown in FIG. 2(b), by applying a negative voltage bias to the input modulated signal Pb that varies within a voltage range between the ground potential (0 V) and the power supply voltage −VL as shown in FIG. 2(a), to adjust it to the bias condition of the transistor FETb that operates under the power supply voltage −VH.
A connection point between the resistor 6a and the Zener diode 7a is connected to the input terminal of the waveform detector 3a. An analysis of whether or not waveform distortions are occurring in the drive signal Pga is automatically performed by supplying an output waveform of the resistor 6a to the waveform detector 3a. 
Furthermore, a connection point between the resistor 6b and the Zener diode 7b is connected to the input terminal of the waveform detector 3b. An analysis of whether or not waveform distortions are occurring in the drive signal Pgb is automatically performed by supplying an output waveform of the resistor 6b to the waveform detector 3b. 
The Zener diode 8a connected between the resistor RLa and the input terminal of the excessive electric current detector 4a, and the Zener diode 8b connected between the resistor RLb and the input terminal of the excessive electric current detector 4b, are provided to detect excessive electric current flowing in the transistors FETa and FETb through the resistors RLa and RLb, respectively.
In other words, the Zener diode 8a forms an excess electric current detection level shifter. This level shifter level-shifts a voltage VRLab (lowered by the falling voltage VRLa occurring at both ends of the resistor RLa with reference to the power supply voltage +VH as shown in FIG. 2(c)) based on the corresponding Zener voltage and supplies it to the excessive electric current detector 4a. Then, as shown in FIG. 2(d), the Zener diode 8a supplies a falling voltage VRLac adjusted to the bias condition of the excessive electric current detector 4a operating under the power supply voltage +VL.
If the falling voltage VRLac becomes larger than a predetermined allowable voltage, the excessive electric current detector 4a detects the occurrence of an excessive electric current and takes necessary steps to stop input modulated signals Pa and Pb in order to prevent a damage to the transistor FETa.
In addition, in a like manner, the Zener diode 8b forms an excess electric current detection level shifter. This level shifter level-shifts a voltage VRLbb (lowered by the falling voltage VRLb occurring at both ends of the resistor RLb with reference to the power supply voltage −VH as shown in FIG. 2(c)) based on the corresponding Zener voltage and supplies it to the excessive electric current detector 4b. Then, as shown in FIG. 2(d), the Zener diode 8b supplies a falling voltage VRLbc adjusted to the bias condition of the excessive electric current detector 4b operating under the power supply voltage −VL.
If the falling voltage VRLbc becomes larger than a predetermined allowable voltage, the excessive electric current detector 4b detects the occurrence of an excessive electric current and takes necessary steps to stop input modulated signals Pa and Pb in order to prevent a damage to the transistor FETb.
As described above, a conventional class D amplifier performs highly efficient power amplification by operating transistors FETa and FETb under high voltage power supply voltages +VL and −VL. Various types of level shifters are also provided which utilize Zener diodes 7a, 7b, 8a, and 8b, so as to perform power amplification in accordance with the respective bias conditions of the semiconductor integrated circuit device 1 that operates under power supply voltages +VL and −VL, and the class D amplifier that operates under power supply voltages +VH and −VH.
Zener diodes 7a, 7b, 8a, and 8b are provided in order for conventional class D amplifiers to perform predetermined operations in accordance with the bias conditions of the semiconductor integrated circuit device 1 and the class D amplifier as described above. In addition, Zener diodes 9a and 9b are provided in order to make different the power supply voltages +VL, −VL for the semiconductor integrated circuit device 1 and the power supply voltages +VH, −VH for the class D amplifier.
Since these Zener diodes 7a, 7b, 8a, 8b, 9a, 9b do not always generate equal Zener voltages for each set due to their electrical and other properties, there were problems of variations in the Zener voltages (manufacturing variations, fluctuations during operation, and the like), hence making it impossible for the class D amplifiers to perform the predetermined operations that are adjusted to the bias conditions described above.
In other words, if variations occur in the Zener voltage between the Zener diode 7a that forms the bias voltage level shifter of the power supply voltage +VH side in FIG. 1 and the Zener diode 7b that forms the bias voltage level shifter of the power supply voltage −VH side in FIG. 1, the bias points of the drive signals Pga and Pgb respectively supplied to the transistors FETa and FETb which operate in a push-pull manner, will shift away from the correct bias as illustrated in FIG. 2(b), causing problems such as waveform distortions in the output modulated signal Pout and the inability to perform efficient power amplification. As a result of the bias points of the drive signals Pga, Pgb shifting away from the correct bias, a load that exceeds the allowable power loss is applied to at least one of the transistors FETa and FETb, which leads to a problem of the transistors being easily damaged.
Even further, even if the Zener voltages of both the Zener diodes 7a and 7b are shifted from the correct Zener voltage, problems will occur such as waveform distortions in the output modulated signal Pout, inability to perform efficient power amplification, and damage to transistors FETa, FETb.
If variations occur in the Zener voltage of the Zener diode 8a that forms the excessive electric current detection level shifter of the positive power supply voltage +VH side, an offset voltage will be applied to the falling voltage VRLac as illustrated in FIG. 2(d) generating a voltage fluctuation and consequently causing a problem of the excessive electric current detector 4a not being able to correctly detect the excessive electric current flowing in the transistor FETa.
If variations occur in the Zener voltage of the Zener diode 8b that forms the excessive electric current detection level shifter of the positive power supply voltage −VH side, an offset voltage will be applied to the falling voltage VRLbc as illustrated in FIG. 2(d), generating a voltage fluctuation and consequently causing a problem of the excessive electric current detector 4b not being able to correctly detect the excessive electric current flowing in the transistor FETb.
When variations in the Zener voltage occur in the Zener diodes 9a and 9b each forming a power supply voltage shifter, a problem occurs in which it becomes impossible to operate the semiconductor integrated circuit device 1 based on the correct voltage of two power supply voltages +VL and −VL.